1. Field of the Invention
The invention relates to analog feedback amplifier circuits which require DC offset correction, and in particular to analog feedback amplifier circuits used to accomplish offset correction while conserving the dynamic range of the signal to be amplified.
2. Description of the Prior Art
DC offset in an analog signal is an often unwanted artifact of component mismatch or other phenomena. DC offset can impair the dynamic range and the integrity of the signal to be amplified.
Correlated double sampling (CDS) is a technique often used to correct for DC offset. In a system using CDS, the amount of DC offset is calculated, stored, and subtracted from the signal before amplification. The DC offset is calculated during an inactive time for the amplifier--when the signal input to the amplifier indicates that the amplifier should not be generating an output.
Under the assumption that the DC offset of the signal during this inactive time is equal to the DC offset during an active time for amplification, the DC offset is calculated during the inactive time. The DC offset calculated is then stored and subtracted from the signal during active periods for the amplifier.
There are various ways to implement CDS, which are known in the prior art. If the analog signal is converted to a digital signal somewhere in the signal path, the sampling of the DC offset can occur in the digital domain and the offset may be stored in one or more digital registers. The benefit of this implementation of CDS is that a digital register provides lasting, stable storage for the DC offset value to be subtracted from the signal.
This implementation has the distinct disadvantage, however, that subtraction only will happen in the digital domain, and therefore dynamic range can be lost in the signal before its conversion to a digital signal. Also, this technique is limited to circuits which include an A/D converter somewhere in the signal path, or requires the addition of an A/D converter solely for this purpose. Moreover, if the system is subject to drifting DC offsets (because of temperature or gain changes, for example) the DC offset stored may not correspond to the actual DC offset after some period of operation.
A variation of this implementation is to convert the DC offset stored in the digital register to an analog value (through a D/A converter) and to subtract this analog value from the signal before it enters the digital domain (and before dynamic range is lost in the analog domain). This solves the problem of lost dynamic range in the analog domain, however the other two problems (limitation to those systems employing conversion to a digital signal and problems due to DC offset drift) are not remedied.
An implementation of CDS that does not require conversion to the digital domain is implemented by calculating the DC offset in the analog domain and storing it in a sample-hold amplifier. This implementation usually involves storing a voltage on a capacitor which corresponds to the amount of DC offset required. It is not necessary that the sample-hold amplifier be a second amplifier in the circuit, a second input stage to the existing amplifier in the circuit may be added instead, and this second input stage, again in conjunction with a capacitor storing a voltage corresponding to DC offset, takes the place of the second amplifier.
However, this implementation has the significant disadvantages that capacitor storage of a voltage corresponding to the DC offset is subject to leakage and is therefore not permanent. Moreover, the prior art circuits used for this implementation often cause outputs of the channel to be corrupted during DC offset cancellation, which may lead to complex timing issues between successive stages needing DC offset correction. This is an especially important issue when offset correction must occur simultaneously across partitioning boundaries in an application.